xilinx - Verilog for error while synthesizing -

when try synthesize verilog project following errors: error:xst:2634 - "shiftman.v" line 15: loop stop condition should depend on loop variable or static. error:xst:2634 - "shiftman.v" line 22: loop stop condition should depend on loop variable or static.

i think understand causes error, can't find way fix it.

module shiftman(in,sh,out);  input[47:0] in; input[8:0] sh; output[47:0] out; reg[47:0] out; reg[7:0] r; reg i; always@(in or sh) begin r=sh[7:0]; out=in; if(sh[8]==0)         for(i=0; i<r; i=i+1)         begin         out[23:0]={1'b0,out[23:1]};         end else         for(i=0; i<r; i=i+1)         begin         out[47:24]={1'b0,out[47:25]};         end  end  endmodule 

the reason synthesis failing because cannot uses variable-iteration loops in synthesizable code. when synthesizing, tool attempt unroll loop, cannot if termination condition loop not static or determinable @ synthesis. condition i <= r such condition cannot unroll loop without knowing r, input module , thus, not static.

in order fix this, youll need rewrite code in way synthesis tool can process. looks of it, logically shifting either top or bottom of in sh[7:0] depending on sh[8]. in order this, don't need looping @ all, can use >> (logical right shift operator). so, always block more this:

always @(*) begin   out = in;    if (sh[8])     out[47:24] = in[47:24] >> sh[7:0];   else     out[23:0] = in[23:0] >> sh[7:0]; end