system verilog - UVM virtual sequencer: choose the right child sequencer -

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i have question virtual sequencer in uvm. let's think have n equal interfaces driven n equal drivers, each 1 connected own sequencer. want have transaction like:

    class my_transaction extends uvm_sequence_item;          logic data;          int num_if;     endclass

that when executed `uvm_do() sent driver number num_if. idea kind of work need virtual sequencer "forward" transaction right sequencer (the number num_if). right? if yes, how done? thanks.

while tudor's answer work technically, conceptually decision on of interfaces run on (num_if) value should not belong transaction, sequence calls (which of course should randomized). transactions should contain representation of value travels b , way in travels protocol. specification of which , b outside of responsibility of transaction.

in case, variation on transaction , tudor's sequence this:

class my_transaction extends uvm_sequence_item;    rand logic data; endclass

..and..

class some_virtual_sequence extends uvm_sequence;   `uvm_declare_p_sequencer(virtual_seqr)   rand int num_if; constraint.....   task body();     my_transaction trans = my_transaction::type_id::create("my_transaction");     start_item(trans, , p_sequencer.seqrs[num_if]);     trans.randomize(); // randomization should done after start_item()     finish_item(trans);   endtask endclass

..running on virtual sequencer tudor says:

class virtual_seqr extends uvm_sequencer;   my_sequencer seqrs[10]; endclass

the above approach lets randomization happen in correct place: after start_item() returns , prior calling finish_item() completes sequence item.


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